1. Field of the Invention
The present invention relates to a test circuit which is suitable for use in a semiconductor integrated circuit wherein a memory device having a wide data bus and logic circuits are mixed together on a single chip and which is provided on the same chip as the semiconductor integrated circuit and used to perform a unit test of the memory device.
2. Description of the Prior Art
FIG. 3 is a circuit diagram showing a conventional test circuit. In the drawing, reference numeral 201 indicates a shift register for successively shifting and writing therein m-bit testing data (input data) inputted from a testing data input terminal 102 in accordance with a clock pulse inputted from a testing data write clock input terminal 103. The shift register 201 is capable of writing data of m-bit.times.n stages (m.times.n bits) (where m and n: 0 or natural numbers) therein. Incidentally, the shift register 201 shown in FIG. 3 shows the writing of data of 8-bit.times.16 stages (i.e., 128 bits) therein. Further, the shift register 201 controls an output, based on a control signal inputted from a testing output control input terminal 108.
Reference numeral 202 indicates a 16-Mbit DRAM (Dynamic Random Access Memory) used as a memory device to be tested. The DRAM 202 inputs or receives addresses (row and column addresses) in accordance with control signals supplied from a testing address input terminal 104, a testing row address strobe input terminal 105 and a testing column address strobe input terminal 106 and writes the testing data of the shift register 201 into or at the input addresses in accordance with a control signal inputted from a testing write control input terminal 107. Further, the DRAM 202 is also provided with the function of controlling an output, based on the control signal (corresponding to a control signal obtained by inverting the control signal inputted to the shift register 201) supplied from the testing output control input terminal 108 in a manner similar to the shift register 201.
Reference numeral 203 indicates a multiplexer for outputting a plurality of input data to a testing data output terminal 101 in response to a selection control signal inputted from a testing data output selection input terminal 109. Reference numeral 204 indicates a wide data bus having a m.times.n bit width (where m: testing data bus bit width of chip and n: internal wide data bus bit width/m), for connecting the shift register 201, the DRAM 202 and the multiplexer 203 to each other. The bit width of the wide data bus 204 shown in FIG. 3 indicates a 8.times.16 (128) bit width.
Incidentally, numerals (4, 8, 12 and 128) assigned to respective wiring or conductors respectively indicate the number of bits of data to be transferred.
Further, D (7:0) and Q (127:0) of the shift register 201, A (11:0) and DQ (127:0) of the DRAM 202, and D (127:0), Q (7:0) and SEL (3:0) of the multiplexer 203 also indicate the numbers of bits of data to be input and output and the number of data input and output terminals, respectively. For example, D (7:0) of the shift register 201 shows the input of 8-bit data therein.
The operation of the present test circuit will next be described.
(1) The operation of writing of testing data into the DRAM 202 will first be explained.
The testing data (input data) inputted from the testing data input terminal 102 is written into the shift register 201 by eight bits for every one clock pulse in response to the leading edge of the clock pulse inputted from the testing data write clock input terminal 103.
Thus, since the 128-bit testing data is written into the shift register 201 (i.e., the Q (127:0) of the shift register 201 from the Q (127:119) to Q (7:0)) by eight bits every one-shot clock pulse, sixteen clock pulses are required to write the 128-bit testing data into the shift register 201.
Although the testing data is successively written into the shift register 201 by eight bits, the testing data written into the shift register 201 is always outputted from the outputs Q (127:0). However, when the shift register 201 is provided with the output control function and the control signal, e.g., H level (corresponding to 1 defined in logic) inputted from the testing output control input terminal 108 is inputted to an output enable input (OE) of the shift register 201, the data written into the shift register 201 is prohibited from being outputted from the Q (127:0) (i.e., the shift register 201 is controlled not to output the data from the outputs Q (127:0)). Since, on the other hand, the control signal indicative of the H level (1) inputted from the testing output control input terminal 108 is inverted by the DRAM 202 and inputted therein (i.e., the DRAM 202 is supplied with L level (0)), the outputs DQ (127 0) of the DRAM 202 are placed in a state in which the DRAM 202 may output data in contrast with the outputs Q (127:0) of the shift register 201 which cannot output data. Thus, the outputs of the shift register 201 and the DRAM 202 are controlled by the control signal inputted from the testing output control input terminal 108 to avoid the collision between the data transferred to the wide data bus 204.
When the testing data (128-bit testing data) corresponding to sixteen clock pulses is written into the shift register 201 by eight bits, the control signal inputted from the testing output control input terminal 108 is changed from the H level (1) to the low level (0). As a result, the outputs Q (127:0) of the shift register 201 are placed in a state in which the shift register 201 may output the testing data, whereby the testing data is outputted from the shift register 201. Thus, the 128-bit testing data written into the shift register 201 is written into the DRAM 202 in one write operation through the wide data bus 204 configured in 128-bit width.
Upon write operation, the DRAM 202 receives L level (0) obtained by inverting the control signal indicative of the H level (1) inputted from the testing write control input terminal 107. Upon read operation, the DRAM 202 receives the H level (1) obtained by inverting the control signal indicative of the L level (0) inputted from the testing write control input terminal 107. Thus, when the 128-bit testing data is written into the DRAM 202, the control signal indicative of the H level (1) is sent to the DRAM 202 from the testing write control input terminal 107.
The 128-bit testing data is written into the corresponding addresses indicative of storage places for the data to be stored in the DRAM 202 in one write operation. It is thus necessary to write the addresses in the DRAM 202 in advance before the writing of the testing data into the DRAM 202. The addresses are inputted from the testing address input terminal 104 as 12-bit address data. When the row addresses of the addresses are inputted to the DRAM 202, the control signal inputted from the testing address strobe input terminal 105 is rendered H in level and its inverted L level (0) signal is inputted to a RAS (Row Address Strobe) of the DRAM 202. When, on the other hand, the column addresses are inputted to the DRAM 202, the control signal inputted from the testing address strobe input terminal 106 is rendered H (1) in level and its reversed L level (0) signal is inputted to a CAS (Column Address Strobe) of the DRAM 202. Upon normal conditions (when no row and column addresses are input), the control signals inputted from the testing row address strobe input terminal 105 and the testing column address strobe input terminal 106 are respectively Low (0) and hence the signal High (1) is inputted to each of the RAS and CAS of the DRAM 202.
The address data sent from the testing address input terminal 104 is represented as 12 bits. The row addresses are represented as combinations of [1,0] corresponding to 12 bits of the address data, i.e., 2.sup.12 rows (4096 rows), whereas the column addresses are represented as combinations of [1,0] corresponding to 5 bits of 12 bits of the address data, i.e., 2.sup.5 columns (32 columns).
(2) The operation of reading of the testing data written into the DRAM 202 (at the time of the determination as to the function of the DRAM 202) will next be explained.
The control signal inputted from the testing output control input terminal 108 is switched to the H level (1) (the inverted signal L level (0) is inputted to the DRAM 202) to thereby bring the DQ (127:0) of the DRAM 202 into a state in which it may output data. Further, the control signal inputted from the testing write control input terminal 107 is switched to the L level (0) (the inverted signal H level (1) is inputted to the DRAM 202) to thereby place the inputs DQ (127:0) of the DRAM 202 in a data read state. The testing data written into the DRAM 202 is read out in one read operation and transferred to the multiplexer 203 through the wide data bus 204.
When the testing data is sent to the multiplexer 203, the testing data output selection input terminal 109 is switched 16 times (n times) to read the testing data into the testing data output terminal 101 of the chip from the multiplexer 203 in units of 8 bits (m bits). Incidentally, the selection control signal inputted from the testing data output selection input terminal 109 includes 4 bits to allow switching between 16 signals. A comparison between the read 8-bit testing data and a prepared 8-bit expected value is performed 16 times (n times) to thereby make a decision as to the function of the DRAM 202.
Incidentally, JP-A-60/185300 is disclosed as a prior art reference related to the present application.
The conventional test circuit has the following problems because it is constructed as described above.
(1) Upon writing the testing data into the shift register 201, the sixteen clock pulses must be applied to the shift register 201. Therefore, a test time interval is spent by these clock pulses.
(2) In order to determine, by the wide data bus, whether the testing data written into the DRAM 202 is normal or abnormal, the selection signal inputted from the testing data output selection input terminal 109 is switched 16 times (n times) to thereby read the testing data from the 8-bit (m-bit) testing data output terminal 101 of the chip. Further, the comparison between the read testing data and the 8-bit (m-bit) expected value must be performed 16 times (n times). Therefore, a further test time interval is spent.
If the testing data output terminal 101 is represented as 128 bits, then the 128-bit testing data can be read from the 128-bit testing data output terminal 101. It is therefore considered that the need for 16-time switching between the signals by the multiplexer 203 is eliminated and the comparison between the testing data and the 128-bit expected value can be performed at one time. However, since limitations are imposed on the number of pins in a package for a semiconductor integrated circuit (IC), the testing data output terminal 101 is dedicated to a testing terminal to the end, and the large number of pins cannot be shared with the testing data output terminal 101, the testing data output terminal 101 is set to 8 bits.